1. Field of the Invention
The present invention relates to a power management system, and in particular, to power management system and power management method capable of controlling the power state of a processor complying with the “Advanced Configuration and Power Interface (hereinafter as ACPI)” specification.
2. Description of the Related Art
ACPI are widely used in current computer systems to allocate system resources and manage the status of each component in the computer system effectively. Functions, such as power management of the system, peripherals, and the processor, and performance management, battery management, temperature management, system event management of the peripherals and the processor, have been defined in the ACPI specification. Further, the software and hardware behavior for implementing the aforementioned functions are also defined in the ACPI specification.
FIG. 1 is a diagram illustrating the power states of a central processing unit (CPU) defined in the ACPI specification. In the ACPI specification, it is defined that the CPU works normally in the working state (e.g. C0 state), such as executing each instruction and task. If the computer system has been idle for more than a certain period of time, the operating system of the computer system may control the CPU to enter one of the low power states, such as states C1˜C4. The operating system may determine which state the CPU may enter according to the bus master activity status (BM_STS). The low power states of the CPU defined in the ACPI specification comprise a first low power state (C1 state), a second low power state (C2 state), a third low power state (C3 state), and a more power-saving fourth low lower state (C1 state), wherein the degree of power consumption decreases from state C1 to state C4. In state C2, the CPU merely monitors the accessing operations of the bus master without executing any instructions, wherein the bus master indicates a component having the bus mastership in the computer system, such as the USB controller, the PCI controller, etc. In state C3, the clocking of the CPU is stopped, and the CPU cannot monitor the accessing operations of the bus master. Compared with state C3, the operation voltage of the CPU is lowered in state C4, so that the CPU may stay in a deeper sleep state. For example, the operation voltage of the CPU is 1.0V in state C0, and the operation voltage of the CPU may be lowered to 0.6V or even lower in state C4.
When the operating system of the computer system has detected that there is no operation in the computer system for more than a certain time period, the operating system may control the CPU to enter state C3 or C4, so that the computer system may save power more effectively.
In state C2, if there is an interrupt event generated or the CPU is requested to execute instructions, the CPU may go back to state C0 from state C2. In state C3/C4, if there is an interrupt event or accessing request of the bus master, the CPU may be awakened to state C0 or C2 from state C3/C4.
Since the operation voltage changes, it may take a very long time (e.g. dozens of microseconds) to enter or exit state C4, thereby causing decrement of system performance. In some applications, it may cause problems of user experience due to the long wait time for entering/exiting state C4. For example, since a USB camera has to transmit data frequently, it cannot tolerate the delay caused by the wait time for exiting state C4. In addition, a high-definition audio device is also a common example, and it may cause noise due to the long delay for exiting state C4. In order to solve the aforementioned issues, the computer system may stop the CPU to enter state C4 when using the aforementioned applications, and thus it is evitable that the power consumption of the computer system is increased.
A power management unit (PMU) is usually used to control the power state of the CPU, and it may require an additional voltage regulator may be required to control the CPU to enter state C4. However, in current computer systems, the voltage regulator and the power management unit operate independently, and the power management unit cannot retrieve the status of the voltage regulator. After the CPU exits the low voltage state (e.g. state C4 defined in ACPI), the power management unit has to control the computer system to wait for a sufficiently long, fixed period of time in order to assure that the voltage level of the CPU has recovered to the stable operation voltage of the working state. However, it may usually cause a reduction of computer system performance.